Statistical delay modeling and analysis for system on chip

Abstract

It is seen that designing using conventional methodologies in Deep Sub Micron geometries, at times, ends up in very pessimistic design and less yield. This is because, today’s tools don’t consider statistical variation of parameters in the fabrication process. IC manufacturer can give probability distribution of such parameters. Using those distributions the tool to be designed will give the probability distribution for delays and slacks. A probabilistic estimation can be made about design functioning in deep sub micron geometries. The delays will have probability distributions based on the parameter variations. These distributions can be found using the way of SPICE simulations. But when circuit complexity increases, these simulations will take a lot of time and it is not the suitable way for large designs. A quick and efficient model has been developed based on MOSFET characteristics. Moreover, a statistical delay model for propagation delay of a gate has also been worked out. Also new methodology and implementation scheme is proposed.