Design and synthesis of asynchronous circuits

Abstract

For a very long time, there has been a requirement of circuits that can overcome the difficulties caused by the delay assumptions involved in a physical system. With decreasing on-chip dimensions of circuits as a result of advancing VLSI technology, delays within the circuit interconnects have become significant. Because of these difficulties, chip manufacturing industry is in search for an alternate design methodologies such as nanotechnology and clock-less (asynchronous) circuits. Asynchronous circuits are low in power consumption, faster in speed, adaptable to newer technologies and have no global timing issues. The bottleneck with the design methodology for such circuits is the lack of automated tools and the complexity of designs. This work attempts to give an alternate synthesis °ow to the implementation of a class of asynchronous circuits, known as delay-insensitive (DI) circuits.

A recent design methodology that claims to synthesize DI circuits is \Null Conventional Logic" (NCL). Using the logical description of the design, one can implement a DI version of the circuit using NCL. As such there is no specialized language for design, verification and synthesis of NCL circuits. This work represents an effort to fill the gap by providing some translation rules for synthesis of such circuits using a language called DISP (Delay Insensitive Sequential Processes) and the NCL design methodology. This work also incorporates the design of a programmable asynchronous shift register. This was done as a part of curiosity and exploration for understanding of the design °ow that the designers usually adopt for analyzing their designs.