Design of a low power, high speed MAC unit

Abstract

MAC operation is the main computational kernel in any digital signal processing architectures. MAC consumes nearly 2/3 portion of total power dissipated in a DSP block. This thesis deals with the design of a low power, high-speed MAC unit using custom based approach. Power-delay product (PDP) is taken as a design metric for this thesis. To meet the objective the first step is to design low power and speed efficient sub-blocks of a MAC unit such as Full Adder, register, multiplexer etc. Five different types of MAC units are designed. They are MAC unit using modified Booth’s algorithm, MAC unit using carry save principle, MAC unit using bypass principle and reconfigurable MAC unit. A performance analysis is drawn among these architectures. MAC unit is implemented using both conventional full adders as well as using a low power, high-speed full adder architecture. Layout of MAC unit architectures are done using Magic tool (0.25µm technology as well as 0.18 µm technology). Power & timing analysis are done using LTSpice & Irsim tool. After simulation it is concluded that MAC unit designed using bypass principle and reconfigurable MAC unit are suitable for low power DSP applications.