Low power and high speed sample and hold circuit

Abstract

In this thesis work the design of a high speed and low power CMOS sample and hold circuit as a front-end block of pipelined analog-to-digital converter is described. The circuit consists of bottom-plate sampling with differential architecture of Operational Transconductance Amplifier. The sample-and-hold circuit has been laid out in 0.18 µm CMOS technology and simulated using MOSIS CMOS BSIM3v3.1 SPICE parameters. The measurement result shows that the SFDR of 65 dB is achieved up to the sampling frequency of 100 MSPS for input signal amplitude of 1.2 Vpp. The sample-and-hold circuit consumes 4.7 mW from a 1.8 volt supply.