Low power microprocessor design

Abstract

This research work tries to reduce the power consumption of a processor with signal processing features. For low power design, focus is on developing ‘Low power synthesizable Register File’, as the initial study shows that there is potential for significant benefit by doing this. Two techniques are proposed and implemented in this work, (1) Compiler Driven Register Access (CDRA) (2) Register Windowing. Here, Register Windowing is an extension to an earlier technique called ‘Register Isolation’. Benchmarks used for evaluating design in terms of power consumption and performance, simulate conditions encountered by the processor in control and DSP applications. After applying various low power techniques, average power reduction obtained across benchmarks is 1.5% and the maximum power reduction obtained is 2.6% when compared to Base Processor which is a customized version of MIPS architecture with signal processing capability.