Zero-aware 6T asymmetrical SRAM cell for low power cache application

Abstract

This thesis walks around the design and analysis of Static Random Access Memories (SRAMs), with optimization of power as center of attention In this dissertation work a novel architecture of 6T SRAM cell has been designed for low power SRAMs. The proposed cell design is asymmetrical, zero sensitive and contains only single bit line for low power operation. The novel structural design is named as zero-aware 6T asymmetrical SRAM cell and the signal swings have been reduced on high capacitive bit-line for power saving purpose. As the data distribution in cache memories are highly inclined toward zeros, the cell has been constructed for low power read ‘0’ and write ‘0’ operations. The work has been carried out at the transistor level circuit where the layouts of necessary block have also been designed. In the thesis work, 256 Kbits memory array has been implemented using standard 6T SRAM cell as well as the novel SRAM cell to perform the calculations of power and delay. The average dynamic power and access delay of the circuit is improved by more than 50% in comparison to the existing standard circuit.