Performance improvement of an out of order processor by decreasing branch mispredictions

Abstract

Superscalar processors are most common in hardware systems ranging from servers to small low power hand held devices. High performance Superscalar processors execute a large number of instructions to exploit Instruction Level Parallelism. In order to improve the performance, a large dynamic instruction window is necessary, which in turn requires accurate branch predictors.

Accurate branch prediction enables large instruction scheduling window. Hence there is an increasing demand for accurate branch prediction beyond the available prediction technology. Previous studies have shown that a branch predictor predicts the branches for a set of benchmarks. Some studies also show that aliasing among the pattern history table can degrade the performance.

However, little research has been done to understand branch behavior and predict its behavior with different techniques. Most of the branches are predictable with the help of simple predictors. An examination of how branches are correlated to each other and how these correlations help to improve prediction accuracy was observed. A FabScalar tool set which can generate supersclar processors of different configurations was used for simulation purpose.