Implementation of different branch prediction schemes on FabScalar generated superscalar processor

Abstract

Performance of modern pipeline processor depends on steady flow of useful instruction for processing. Branch instruction in the program disrupts the sequential flow of instruction by presenting multiple paths through which program may proceed. By predicting branch outcome early, branch predictor allows processor to continue fetching instruction from the predicted path. As the computer architecture try to squeeze more performance out of superscalar processor by increasing issue widths and pipeline depths. At that time penalties due to branch instruction continue to rise. Because of high branch miss prediction penalty, the branch prediction accuracy is a very important factor for superscalar processor.

This study is concerned about exploring a FabScalar Tool for automatically generating superscalar cores of different pipeline widths, depths and sizes. This tool provides the RTL code of the desired superscalar core. A four issue wide superscalar core is generated using FabScalar tool. On this superscalar core the implementation and comparative study of three different dynamic branch predictions technique is done. These techniques are Bimodal Branch Predictor, Two-way Correlating Branch Predictor and Hybrid Branch Predictor.