Reconfigurable hardware implementation of image processing techniques

Abstract

Nowadays, wearable devices are becoming increasingly popular in everyday lifedue to the advances in body sensor network. The primary concern of these devicesis the power consumption that has implications on the lifetime of battery,form factor, etc. An energy efficient platform is developed as an in-house projectaddressing the computational needs of such devices. Due to the reconfigurablenature of the architecture, the platform has the capability to map multiple frequentlyused Digital Signal Processing (DSP) functions thereby limiting the gatecount as opposed to its dedicated accelerator counterpart. Minimizing the gatecount is desirable in case of low power and low voltage applications.In this work, we explore the possibility of mapping image processing algorithmson the architecture. The smoothing operation and DCT operation are mapped onthe architecture. This poses a large memory requirement owing to store image,hence we further focus on developing multiple controllers for the peripheral interfacesthat enables the architecture to interact with the external environment,thereby eliminating the memory constraint. The interface is used to transfer, postprocess(when necessary) and display the data processed by the proposed architectureon external devices like computer or display panel. The two interfacesdeveloped are VGA interface and UART interface. The architecture require 2304clock cycles for smoothing �16 16� sub-block of a grayscale image whereas theRMS error between the resultant image and MATLAB processed image is 0.8673.The architecture require 336 clock cycles to obtain the DCT of �8 8� sub-block ofa grayscale image. The error between the hardware computed DCT andMATLABcomputed DCT of a Lena intensity image of size �128 128� is quantified by L2norm which comes out to be 2.0214 for a compression of 84%.