Design and Simulation of Single Electron Transistor based SRAM and its Memory Controller

Abstract

"Heterogeneous 3-D integration of single electron transistor (SET) circuits with CMOS based circuits is achieved by stacking a SET layer above CMOS IC. Low power circuit and delay efficient circuits can be designed using SET rather using CMOS. In the research work, we have designed and simulated 6T SRAM array operating at room temperature and at the CMOS comparable voltage. Peripheral circuits like sense amplifier, decoder, write circuit and pre-charge circuit using SET have been designed for optimum performance. Analysis of all the peripheral circuits has been done for power and delay. The stability of 6T SRAM cell is verified using N-curve method. The designed SET based 64-bit SRAM with memory controller can be characterized with read and write access time being 117 ps and 10 ps respectively, with the total average power consumption being 830 nW during read and write operation. Similarly for 64-bit SRAM with memory controller using 16nm CMOS technology has read and write access time 547 ps and 129 ps respectively with the total average power consumption being 182 ?W during read and write operation. The designed SET based SRAM is 99.54% power efficient, 92.19% faster in write access time and 78.58% faster in read access time compared to 16 nm CMOS based SRAM. The maximum frequency of operation for SET based SRAM with memory controller is 4 GHz and for 16 nm CMOS based SRAM it is 1"