FPGA Implementation of an Improved Proportionate Normalized Least Mean Square Algorithm

Abstract

"Adaptive algorithms find various applications in signal processing to estimate unknown signal statistics. Using the error signal as feedback, the filter’s efficients are updated and equals the unknown system coefficients. These algorithms can be implemented on digital signal processing (DSP) processors, field programmable gate array (FPGA) and application specific integrated circuit (ASIC). FPGA offers many benefits over DSP processors, which includes urthermore reduction in latency, increment of throughput and omputational density. FPGA design cycle costs less time and money compared to ASIC implementation.

In this thesis, performance of different adaptive algorithms have been compared in MATLAB tool. 4-tap improved proportionate normalized least mean square (IPNLMS) algorithm is implemented on spartan-3E (XC3S500E) FPGA and compared with results from MATLAB implementation. To transfer results from FPGA to laptop, universal asynchronous receiver and transmitter (UART) integrated circuit that supports serial communication channel is used. An architecture of 4-tap IPNLMS algorithm uses 34864 equivalent gates. An architecture of 4-tap IPNLMS algorithm achieves maximum frequency of 19.86 MHz on spartan- 3E FPGA platform as seen in timing report and takes one cycle to compute one iteration. An architecture of 32-tap IPNLMS algorithm is simulated on XILINX tool due to lack of hardware resources on XC3S500E FPGA and results are reported. Enhancement of this work in term of hardware usage is possible by memultiplexing the similar hardware blocks of this architecture."