Design and implementation of low power superscalar processor

Abstract

As the Reduced Instruction Set Computing (RISC) philosophy architecture provides higher operating frequency and low power design as compared to Complex Instruction Set Computing (CISC) philosophy, a single core superscalar processor is realised. The processor is designed with keeping its application as a low-end budget low power in mind. This M.Tech thesis presents a superscalar processor with 10 stage pipeline architecture and 0.8 Hz of operating frequency. This design is a 4 issue, 6 fetch design with capabilities to avoid hazards such as WAR and WAW hazards by register renaming technique. RAW hazard is avoided by inserting bubbles in the execution as per required. Control hazards are avoided branch predictor. Structural hazards are avoided by shutting down stages previous to that particular stage if there is no sufficient space available to store any data in that particular stage. To reduce power consumption, this design uses concepts like clock gating and common power format