Design of leaf cell layouts for memory compiler

Abstract

Digital layouts are designed in such a way that it should have minimum area and hence lesser delay.On the contrary analog layouts are made using best matching technique so as to provide same environment to each transistors.In this project standard cells have been designed in 90nm and 28nm technology.The challenges faced in making layouts in both technology node have been discussed.My work involves design of leaf cells layouts in 28nm technology for memory compiler for given 32 bit memory array.To store the data, there is a need of memory array. user requirement.Integrating memory with designed leaf cells is done such way that on abutment connection will take automatically with the pins.For this most important is pin placement and top level routing.The inputs to the memory compiler are designed in this project which includes the following leaf cell blocks such as Pre-charge and mux block,Sense amplifier block,Input driver circuit,Output driver circuit,Control block and decoders.All the leaf cells are DRC,LVS and compatability clean and are interconnected in the top level.The bit cell of the memory is not designed since the layout designing of the leaf cell will not match the DRC's.because all the fabs will have their own DRC's designing the bit cell of memory.Hence the above SRAM architecture is designed with minimum area and leaf cells abutting. Practically the area of above design came to be roughly 1023.359 um2.